ADC

The STM32F401RE has a 12 bit 2,4 Msps ADC and this is the peripheral used to collect the pixel values from the CCD.

The output from the CCD is clocked out at 1/4 of frequency of the master clock eg. 0,50 MHz. To accurately sample at this rate the ADC is triggered by a timer (TIM4) running at this frequency.¹

The ADC runs with a clock of 36 MHz. That means each cycle takes:
(36 MHz)⁻¹ = 28 ns

It’s a 12 bit ADC, and each bit takes one cycle, so the conversion process itself of course takes:
12·28 ns = 0,33 µs

The output-rate is 0,50 MHz, so the total conversion time cannot exceed:
(0,50 MHz)⁻¹ = 2,0 µs

With 0,33 µs for a 12-bit conversion, there’s 1,67 µs to sample in. This gives a sampling time (in ADC clock cycles) of:
1,67 µs / 28 ns = 60

Reading through the datasheet we find the nearest available setting is 56 cycles. However, I’ve seen no improvements in S/N above 15 cycles, so the ADC sampletime is set to 15.

The converted values are stored in memory using DMA.


Suggested reading:

Application note AN4073 from ST.


The original posts at erossel.wordpress.com:
Reading the TCD1304 with a STM32 Nucleo F401re
More on the Nucleo F401RE’s ADC


¹ Read more about this in the Timers section.

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