The STM32F401RE has a 12 bit 2.4 Msps ADC and this is the peripheral used to collect the pixel values from the CCD.
The output from the CCD is clocked out at 1/4 of frequency of the master clock eg. 0.50 MHz. To accurately sample at this rate the ADC is triggered by a timer (TIM4) running at this frequency.¹
The ADC runs with a typical frequency of 30 MHz. That means each cycle takes:
(30 MHz)⁻¹ = 33 ns
It’s a 12 bit ADC, and each bit takes one cycle, so the conversion process itself of course takes:
12·33 ns = 0.40 µs
The output-rate is 0.50 MHz, so the total conversion time cannot exceed:
(0.50 MHz)⁻¹ = 2.0 µs
With 0.40 µs for a 12-bit conversion, there’s 1.6 µs to sample in. This gives a sampling time (in ADC clock cycles) of:
1.6 µs / 33 ns = 48
The ADC needs about 2 µs to stabilize between each conversion (tstab), so the sampling time (in ADC clock cycles) shrinks to:
(2.46 µs – 2 µs) / 33 ns = 13
Reading through the datasheet we find the nearest available setting is 28 cycles. However, I’ve seen no improvements in S/N above 15 cycles, so the ADC sampletime is set to 15.
The converted values are stored in memory using DMA.
Application note AN4073 from ST.
¹ Read more about this in the Timers section.