Timing requirements

The datasheet for the TCD1304 is at best a little cryptic, so I will try to explain it as best I can.

The TCD1304 needs three driving pulses:

  • fM – the master clock, must run at 0.8-4 MHz
  • SH – the shift gate
  • ICG – the integration clear gate

The datasheet provides the following timing chart to illustrate their function:


The TCD1304’s timing chart.

From this we learn the following (some points are more obvious than others):

  • The data-rate is 1/4 of fM
  • Pixels are only moved to the shift registers when ICG and SH coincide. If SH runs with a shorter period than ICG, the CCD runs in electronic shutter mode, and SH serves to control the integration time.
  • The shortest integration time is 10 µs

Looking closely at the four lines in the timing chart you’ll notice that only ICG, fM and OS are “cut”, so in this timing chart SH has a different time-scale than the others. The SH-pulse is running independently of fM. It’s clarified in the following diagram:


SH- and ICG-pulses only. For some reason my pdf-viewer didn’t catch the “µ” in “10µs”.

The datasheet gives the following timing requirements for the three pulses:


Timing requirements for the TCD1304’s driving pulses.

This translates to:

  1. SH must go high with a delay (t2) of between 100 and 1000 ns after ICG goes low.
  2. SH must stay high for (t3) a minium of 1000 ns.
  3. ICG must go high with a delay (t1) of minimum 1000 ns after SH goes low.
  4. ICG must go high when fM is high (I’m not sure this is actually needed).

This is all handled by the STM32F401RE’s timers.

Suggested reading:
Toshiba application notes for linear CCDs.
Datasheet for TCD1254
Datasheet for TCD1254

The original posts at erossel.wordpress.com:
Driving the TCD1304 with a Nucleo-F401RE